CMOS device performance can be improved by reducing the gate length and/or by increasing the carrier mobility. To reduce the gate length, the device structure must have good electrostatic integrity. It is known that single-gate ultra-thin body MOSFETs, and multiple-gate MOSFETs, such as FinFET and tri-gate structures, have better electrostatic property compared to conventional bulk CMOS devices.
Co-assigned U.S. Pat. No. 6,911,383 to Doris et al. discloses a process to integrate both planar ultra-thin body SOI MOSFET, and FinFET devices on the same wafer. In accordance with this disclosure, the structure is fabricated by a method that includes the steps of providing a SOI structure comprising at least a top semiconductor layer located on a buried insulating layer, the top semiconductor layer having at least one patterned hard mask located in a FinFET region of the structure and at least one patterned hard mask located in a FET region of the structure; protecting the FET region and trimming the at least one patterned hard mask in the FinFET region; etching exposed portions of the top semiconductor that are not protected with the hard mask stopping on the buried insulating layer, the etching defining a FinFET active device region and a FET active device region, the FinFET active device region being perpendicular to the FET active device region; protecting the FinFET active device region and thinning the FET active device region so that the FET device region has a height that is less than the height of the FinFET active device region; forming a gate dielectric on each exposed vertical surface of the FinFET active device region, while forming a gate dielectric on an exposed horizontal surface of the FET device region; and forming a patterned gate electrode on each exposed surface of the gate dielectric.
The term “ultra-thin” is used throughout the present application to denote a thickness of about 30 nm or less. The term “tri-gate” is used throughout the present application to denote a tri-gate device that comprises three conducting channels, one top surface and two vertical surfaces of the Fin. The term “FinFET” is used throughout the present invention to denote a double gate device that comprises a tall, yet thin vertical channel region.
It is known in the art that carrier mobility depends on surface orientation. For instance, electrons are known to have a high mobility for a (100) surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on a (100) surface are roughly 2×-4× lower than the corresponding electron hole mobility for this crystallographic orientation. Co-assigned U.S. Patent Application Publication No. 2004/0256700, discloses a method to integrate these two surfaces on the same wafer such that planar MOSFETs are built on the high mobility surface. That is, nFETs are built on a (100) surface and pFETs are built on a (110) surface. In accordance with this disclosure, a hybrid substrate having a surface of different crystal orientations is provided by wafer bonding two wafers having different crystallographic orientations, masking, etching through one wafer to the other wafer to expose a surface thereof and regrowth of a semiconducting material having the same crystallographic orientation as the exposed surface.
When a tri-gate is fabricated on a standard (100) wafer with the alignment wafer flat parallel to the <110> direction, mixed surface orientation for the channels are formed if the gate is oriented in parallel to the wafer flat. See, for example, FIG. 1A, This tri-gate device structure cannot provide optimum mobility for n-type or p-type MOSFETs. An optimum n-type tri-gate FET can be obtained by fabricating an n-type tri-gate FET on a standard (100) wafer with the alignment wafer flat parallel to the <110> direction and the gate is oriented at 45 from the alignment wafer flat. See, for example, FIG. 1B. Alternatively, an optimum n-type tri-gate FET can be obtained by fabricating an n-type tri-gate FET on (100) wafer with the alignment wafer flat parallel to the <100> direction and the gate oriented parallel to the wafer flat. See, for example, FIG. 1C. An optimum p-type tri-gate FET can be obtained by fabricating a p-type tri-gate FET on (110) wafer with the alignment wafer flat parallel to the <110> direction and the gate oriented parallel to the alignment wafer flat. See, for example, FIG. 1D.
Presently, it is possible to layout the n-type FinFET and the p-type FinFET by an angle of 45° on a (100) surface oriented wafer to obtain high mobility nFETs and pFETs, such a layout, however, is not preferable using today's lithography technology. Moreover, this approach cannot simultaneously provide high mobility planar/multi-gate nFETs and pFETs. Instead, it is desirable to provide a method in which the gate of the nFET and the pFET devices are both oriented in the same direction and yet all channels are on high mobility surface for both nFET and pFET. There is no known prior art that is presently capable of achieving this requirement.
Hence, a substrate structure and a method of fabricating the same are needed to make planar and/or multiple-gated MOSFETs, such as FinFETS and tri-gate MOSFETs, in which all of the channels are oriented on high mobility surfaces with the gate at same direction.